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    • 专利摘要:
    SET OF CIRCUITS FOR ACTIVE CABLE. The present invention relates to circuits, methods and devices that allow signals that are compatible with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention provides a connector that provides signals compatible with a legacy pattern in one mode and a new pattern in another mode.
    公开号:BR112012030352B1
    申请号:R112012030352-0
    申请日:2011-06-30
    公开日:2020-12-29
    发明作者:William P. Cornelius；William O. Ferry；James E. Orr
    申请人:Apple Inc；
    IPC主号:
    专利说明:

    CROSS REFERENCE TO RELATED ORDERS
    [0001] This application claims the benefit of United States Provisional Patent Applications No. 61 / 360,436, filed on June 30, 2010, 61 / 360,432, filed on June 30, 2010, and 61 / 446,027, filed on 23 February 2011, and is related to United States copending patent application No. 13 / 173,979, filed on June 30, 2011, entitled Distribution of Energy within the Cable, which is incorporated by reference. BACKGROUND
    [0002] Electronic devices often include connectors to provide ports where power and data signals can be shared with other devices. These connectors are often designed to be compatible with a standard, such that electronic devices can communicate with each other in a secure manner. The various standards Universal Serial Bus (USB), Express Peripheral Component Interconnection (PCIe) and DisplayPort (DP) are some examples.
    [0003] When necessary, the standards using these connectors are replaced by new standards. As a result, multiple connectors that provide similar functions are often included in an electronic device. For example, many televisions today include HDMI, S-video, component video, and RCA jacks.
    [0004] The inclusion of these connectors increases the size, complexity and cost of the device. Also, the inclusion of multiple options can cause confusion and frustration for customers when they try to determine the best way to configure a particular system.
    [0005] Some of these confusions can be reduced if a connector is capable of providing signals for more than one standard. For example, if a connector can provide signals for both a legacy standard and a new standard, the number of connectors on an electronic device can be reduced, thus allowing the device to be smaller, simpler and less costly.
    [0006] However, however facilitating this may be, it is very difficult to do so. For example, circuits associated with one pattern can interfere with circuits associated with another pattern. This becomes even more difficult when data rates are high, as reflections and termination incompatibilities caused by unused circuits impair the performance of the circuits being used.
    [0007] For example, a new faster standard can share a connector with a slower legacy standard. The circuitry required for the legacy standard can cause reflections and termination incompatibilities for the circuits to the new faster standard, thereby degrading system performance.
    [0008] Thus, circuits, methods and devices are needed to allow several standards to share a common connector. SUMMARY
    [0009] Consequently, the modalities of the present invention provide circuits, methods and devices that allow signals that are compatible with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention can provide a connector that provides signals compatible with a legacy standard in one mode and a new standard in another mode. Typically, the legacy pattern is slower, while the new pattern is faster, although this is not always true.
    [00010] In an exemplary embodiment of the invention, the pins for the new standard can be arranged to achieve at least two objectives. First, they must be arranged to reduce cross-line and interference between them. This can be accomplished by placing several ground pins between the high speed differential signal paths. Second, circuitry can be added in such a way that interference from the circuits to the legacy standard is minimized. This can be done by reducing reflection and impedance mismatch.
    [00011] An exemplary embodiment of the present invention is capable of providing multiple data patterns through the incorporation of various characteristics. In an exemplary embodiment of the present invention, devices that are compatible with the new standard may be able to determine whether they are communicating with a device that is compatible with a legacy standard, or a new standard. This can be done by a first device by detecting voltages or impedances provided by a second device.
    [00012] In various embodiments of the present invention, when two devices in communication are able to communicate with the new standard, this standard can be used for both devices. Where a device is only capable of working with the legacy standard, that standard can be used for both devices.
    [00013] Modalities of the present invention may provide circuits to isolate unused circuitry for one pattern from operating circuitry to the other pattern. In a specific example, resistors, PiN diodes, multiplexers or other components or circuits can be used to isolate two transmitting circuits from each other. Coupling capacitors and inductors can be used as DC blocks and AC filters to isolate circuits.
    [00014] Various embodiments of the present invention can incorporate one or more of these and other features described here. A better understanding of the nature and advantages of the present invention can be obtained by reference to the following detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
    [00015] Figure 1 illustrates a legacy system that can be improved by incorporating modalities of the present invention; figure 2 illustrates a computer system according to an embodiment of the present invention; figure 3 shows a pinout of a connector according to an embodiment of the present invention; figure 4 illustrates circuits and methods used in determining the types of devices in communication with each other according to an embodiment of the present invention; figure 5 shows an active cable according to an embodiment of the present invention; figure 6 shows an active cable according to an embodiment of the present invention; figures 7A to 7C illustrate circuits that can be used to allow signal paths from two different patterns to share common pins of a connector; figures 8A and 8B illustrate alternating circuits that can be used to allow signal paths from two different patterns to share common pins of a connector; figure 9 illustrates circuits and methods used by devices in determining which types of devices they are connected to; figure 10 illustrates a set of circuits for cable attached according to an embodiment of the present invention; and figure 11 illustrates a method of calibrating a cable and related circuitry according to an embodiment of the present invention. DESCRIPTION OF ILLUSTRATIVE MODALITIES
    [00016] Figure 1 illustrates a legacy system that can be improved by incorporating modalities of the present invention. This figure illustrates a computer 110 communicating with a legacy display screen 120 over a legacy connection 115. In a specific embodiment of the present invention, legacy connection 115 is a DisplayPort connection, although in other embodiments of the present invention other connections may be used.
    [00017] In this figure, connection 115 is shown as a legacy connection. In other embodiments of the present invention, connection 115 may also be a new type of connection. Also, while computer 110 is shown communicating with display screen 120, other types of connections can be improved by incorporating modalities of the present invention. For example, a connection can be provided between a portable media player and a display screen, a computer and a portable media player, or among other types of devices. In various embodiments of the present invention, computer 110, display screen 120 and other devices shown or described can be manufactured by Apple Inc. of Cupertino, California.
    [00018] Again, it may be desirable for computer 110 to be able to trigger either a legacy display screen, such as display screen 120, or any other new computer, display screen or other type of device. This typically requires adding another connector to computer 110. This may be undesirable as it increases the complexity, cost and size of computer 110. Adding another connector can also add to consumer confusion.
    [00019] Consequently, embodiments of the present invention can provide a new connector using the same connector as legacy connection 115. An example is shown in the following figure.
    [00020] Figure 2 illustrates a computer system according to an embodiment of the present invention. This figure, like the other figures included, is shown for illustrative purposes and does not limit the embodiments of the present invention or the embodiments.
    [00021] This figure illustrates computer 110 communicating with computer or display screen 220 over high speed connection 225. Computer or display screen 220 communicates with disk unit 230 over high speed connection 235. Computer 110 can use the same connector to form a legacy connection 115 in figure 1 and high speed connection 225 in figure 2. As shown, the high speed connection provided by computer 110 can be daisy-chained to multiple devices. In this configuration, each high speed connection 225 and 235 shares the available bandwidth on the computer connector 110.
    [00022] By providing a connector on computer 110 that can support legacy connection 115 in figure 1 and high speed connection 225 in figure 2, the number of connectors on computer 110 is reduced. This reduces the size of the device, saves money and reduces consumer confusion. In this example, computer 110 communicates with computer or display screen 220 and disk unit 230. In other embodiments of the present invention, other types of devices can be employed. For example, computer 110 can trigger a display screen from an all-in-one computer, a second computer, an independent monitor, an expansion device, a raid driver, or other type of device.
    [00023] An embodiment of the present invention can explain at least two considerations when providing pinouts for a high speed connection using an existing legacy connector. First, signals on different channels of the high-speed connection can be arranged so that they do not interfere with each other. That is, the cross line between high-speed signals can be reduced and signals can be isolated. Second, the circuitry for driving and receiving the new high-speed signals and the circuitry associated with the legacy standard can be isolated to limit interference between them. An example is shown in the following figure.
    [00024] Figure 3 illustrates the pinout of a connector according to an embodiment of the present invention. In this example, DisplayPort is the legacy standard, which has been pinned over to a new standard. This new standard can be referred to as T29, but it is generally identified elsewhere in this document as HSIO. In other embodiments of the present invention, other patterns can be used. Also, one or both of these patterns can be legacy patterns, or one or both of these patterns can be new patterns. Also, while two patterns are shown here sharing a connector, in other embodiments of the present invention, other numbers of patterns can share a connector.
    [00025] In various embodiments of the present invention, the two patterns can be separate and unrelated. In other embodiments of the present invention, they can be related. For example, HSIO can be a high-speed signaling technique that carries DisplayPort information. That is, DisplayPort information can form a tunnel using HSIO signals. HSIO can also carry other types of signal information at the same time, such as PCIe information. In this way, the connector in figure 3 can carry DisplayPort signals directly, or it can carry DisplayPort information that is transmitted as HSIO signals. It should be noted that in the various embodiments of the present invention described below, HSIO is also referred to as T29.
    [00026] In this arrangement, the high speed input and output pins can be isolated from each other. Specifically, high speed receiving signals can be positioned on pins 4 and 6, and 16 and 18. Each of these signal pairs can be isolated by signals that are AC grounds. For example, high speed receive pins 4 and 6 can be isolated by hot plug detection of pin 2 and ground pin 8. Similarly, high speed receive pins 16 and 18 can be isolated by ground 14 and power pin. 20. High speed transmission pins 3 and 5, and 15 and 17, can be isolated by ground pins 1, 7, 13 and 19.
    [00027] Some or all of the ground pins, such as pins 1 and 7, can be AC grounds, compared to a direct DC connection to ground. That is, these pins can be coupled through a capacitor to the ground. This provides a ground connection at high frequencies, while providing an opening at low frequencies. This arrangement allows energy sources to be received at these pins, while maintaining a high frequency ground.
    [00028] In a specific embodiment of the present invention, pin 20 on the first end of the cable connects to pin 1 on the second end of the cable. This allows the power provided on pin 20 by a main device to be supplied to pin 1 on a device connection. Since pin 1 is coupled to ground via a capacitor, DC power can be received, although pin 1 provides AC ground.
    [00029] Also in this arrangement, high-speed signals in the high-speed HSIO standard can share pins with appropriate signals from the legacy DisplayPort standard. Specifically, the high-speed receive signals on pins 4 and 6 can share pins with configuration signals in the DisplayPort standard. High speed receiving signals on pins 16 and 18 can share pins with auxiliary signals in the DisplayPort standard. High-speed transmission signals on pins 3 and 5 can share pins with DisplayPort output signals, as can high-speed transmission signals on pins 15 and 17.
    [00030] Since these connectors can support devices using both DisplayPort and HSIO standards, there are at least four possible configurations when two devices communicate with each other. For example, a primary DisplayPort device can communicate with a DisplayPort or HSIO device. Also, a main HSIO device can communicate with either a DisplayPort device or another HSIO device. Consequently, devices compatible with the new HSIO standard may be able to determine which type of device they are communicating with. Once the configuration is known, the devices can be configured appropriately. An example is shown in the following figure.
    [00031] Figure 4 illustrates circuits and methods used in determining the types of devices in communication with each other according to an embodiment of the present invention. On line 410, a DisplayPort source or host is communicating with a DisplayPort heatsink or end. A DisplayPort source or host provides pull-down resistors on CFG 1 and CFG2 configuration pins. In this example, the pull-downs are shown as 1 Mega in size, although this can vary in shape according to the modalities of the present invention. The DisplayPort source or host is connected via a passive cable to a DisplayPort heatsink or end. The DisplayPort heatsink or end can function as a DP device.
    [00032] On line 420, a DisplayPort source or host communicates with an HSIO heatsink or end. In that particular embodiment of the present invention, an HSIO heatsink or end will not work under these conditions, although in other embodiments of the present invention, when the HSIO heatsink or end is a display screen, the HSIO heatsink or end may act as a DisplayPort sink or end.
    [00033] On line 430, a cable adapter is connected to the DisplayPort source or host. The cable adapter has a pull-up on the CFG2 configuration pin that is much smaller than the pull-down resistor at the source or host. Consequently, the voltage at the CFG2 configuration pin is raised to a high degree. The cable adapter can provide signals for an HDMI or DVI type of the heatsink or end.
    [00034] On line 440, an HSIO source or host communicates with a heatsink or DisplayPort end via a passive cable. The HSIO source or host has pull-downs on the CFG1 and CFG2 configuration pins. In this example, the pull-down resistors have a value of 1 Mega, although other sizes of resistors can be used according to the modalities of the present invention. In this case, the HSIO source or host does not detect a pull up on the CFG2 configuration pin, and consequently the HSIO source or host functions as a DisplayPort device.
    [00035] On line 450, an HSIO source or host communicates with an HSIO heatsink or end. In this configuration, an active cable is required between the HSIO source or host and the HSIO heatsink or end. The active cable has a 100K pull up on the CFG2 pin, which provides a high voltage on the CFG2 pin. Both the HSIO source or host and the HSIO heatsink or end detect this level and can function as an HSIO device.
    [00036] On line 460, a cable adapter is connected to an HSIO source or host. The cable adapter has a pull up on the CFG2 configuration pin that is much smaller than the pull down resistor at the source or host. Consequently, the voltage at the CFG2 configuration pin is raised to a high degree. The adapter cable can provide signals for an HDMI or DVI type of the heatsink or end.
    [00037] In various embodiments of the present invention, it is desirable to increase the level of energy provided by the source of the host or heatsink or end. In a specific embodiment of the present invention, this is achieved using an LSx bus, as further described below. In another specific embodiment of the present invention, this is achieved by providing a 1 K pull down on the configuration pin CFG1 on the cable. This is detected by the HSIO source or host and HSIO heatsink or end, for example, by supplying a small current to the configuration pin. If the voltage remains low, the pull-down resistor is small, and a high voltage mode is enabled. If the resistance of the pull-down resistor is high, the resulting voltage will be high, and the high voltage mode will not be enabled.
    [00038] In various embodiments of the present invention, it is desirable to leave this high energy mode under some circumstances in order to protect connected devices. Consequently, if a cable is pulled, power is withdrawn from a device, or another similar situation occurs, one can leave the high energy stage. In a specific embodiment of the present invention, the low energy state may include providing a supply voltage of 3.3 V, while the high energy state may include providing a supply of 12 volts. In various embodiments of the present invention, these voltages can be different, and they can also vary depending on various conditions, such as the amount of line loss. In addition to saving energy, the cable can enter a sleep mode as soon as a period of inactivity is detected.
    [00039] Again, to support a high speed standard, an active cable may be required. This cable must have the ability to time-delay data at each of its ends in order to provide data that is easily recoverable by an HSIO source or host and an HSIO heatsink or end. An example of such a cable is shown in the following figure.
    [00040] Figure 5 illustrates an active cable according to an embodiment of the present invention. For simplicity, only circuitry with high speed operation is shown. This cable includes two active plugs 500 and 505, one at each end of the 507 cable. Each active plug includes two clocks and data recovery circuits for timing data. Specifically, the active plug 500 provides high speed transmission signals 3 and 5, and receives high speed signals on pins 4 and 6. A cable microcontroller 520 can be used to configure clock and data recovery circuits 510 and 530 on an active 500 plug.
    [00041] Similarly, active plug 505 provides high-speed transmission signals on pins 3 and 5, and receives high-speed signals on pins 4 and 6. A 550 cable microcontroller can be used to configure clock and recovery circuits. data 540 and 560.
    [00042] The clock and data recovery circuits can provide and receive signals in a variety of formats. For example, these circuits can include optical receivers and transmitters, so that cable 507 becomes a mixture of optical fiber and electrical wires.
    [00043] In various embodiments of the present invention, the clock and data recovery circuits can employ equalizer circuits, buffers, emphasis and de-emphasis circuits as appropriate. Also, loopback paths can be included for diagnostic purposes. For example, the CDR output 510 can be connected as an input for CDR 530, while the CDR output 540 can be connected to an input for CDR 560. This loopback path allows an HSIO device to determine the location of transmission errors when they They emerge. This loopback path can also be used in calibration or training routines, as described below. In other modalities, the cable can communicate with itself from end to end for diagnostic purposes. Other features that can be included for diagnostics include eye size measurements.
    [00044] In various embodiments of the present invention, the cable can be configured. In that specific embodiment of the present invention, the circuitry on the cable plug 500 can be configured using cable microcontroller 520, while the circuitry on the cable plug 505 can be configured using cable microcontroller 550. In other embodiments of the present invention , other circuits were used to configure one or both plugs 500 and 505.
    [00045] In this specific embodiment of the present invention, operating parameters, modes and other aspects and characteristics of the plug circuit set can be configured. Information for this configuration can include parameters for control, diagnosis, testing, configuration, circuit monitoring, as well as other parameters. The ability to configure a cable in this way allows the cables to adapt to new hosts and devices as the cable is used in various system applications.
    [00046] Information regarding the identification of the cable type, supplier, and other identification information may be available from hosts or devices and cables. The exchange of this information can be used to properly configure and trigger the circuitry on hosts or devices as well as on cables.
    [00047] In this specific embodiment of the present invention, configuration and identification information can be read from and written to the cable using LSx signals on pins 9 and 11, although in other embodiments of the present invention, other signal pins can be used.
    [00048] In various embodiments of the present invention, the code on cable microcontrollers 520 and 550 can be changed, reconfigured, improved or updated. This code can be encrypted for security reasons. Also, data provided during a code change, reconfiguration or enhancement can also be encrypted.
    [00049] Also in various embodiments of the present invention, cable microcontrollers can be in communication with port microcontrollers on devices (not shown) that are communicating over the cable. In a specific embodiment of the present invention, a port microcontroller in a first device can communicate directly with a cable microcontroller in the plug inserted in the first device, as well as a port microcontroller in a remote device coupled to the remote plug. Additional communication can be obtained with the remote or extreme plug "returning" messages from the port microcontroller on the remote device.
    [00050] These communications between cable and port microcontrollers can take various forms. Traditionally, interconnections have been fixed at each end, with few opportunities to discover improved capabilities or flexible implementations. Consequently, embodiments of the present invention provide this communication capability, so that, for example, a cable can share information regarding its characteristics to a host or device, and the host or device can use those characteristics.
    [00051] In other examples, such communications between the various ports and cable microcontrollers may be of a diagnostic nature. These diagnostic communications can assist in fault isolation, by one end user or another, which can allow quick repair of problems and can focus attention on devices that are causing the failure. These communications can also be useful in testing and manufacturing. They can also be used to optimize the setting for energy saving, for example, a channel that is not being used can be turned off, a remote low-power device can be turned on by a host, so the device does not require a connection to a wall outlet. Also, energy consumed by remote devices can be monitored, and energy increases (or decreases) can be allowed when necessary. They can also allow devices to continue to function despite a number of defects. They may also allow the use of copper or another conductor, or optical fibers in the cable itself.
    [00052] Again, in various embodiments of the present invention, a cable can provide pull-ups on the configuration pins CFGl and CFG2, while the devices coupled by the cable can provide pull ups on its LSR2PTX pins. (The pull-up on an LSR2PTX pin can be seen by a remote device on its LSP2R RX pin due to the crossing of these lines on the cable, as shown). The CFG2 pull-up can allow a device to determine that a cable is attached, even when there is no remote device. In a specific embodiment of the present invention, when a cable is present without a remote device, a nearby device may communicate with a cable microcontroller in its plug, but may not be able to communicate with a cable microcontroller in the remote plug, since there is no remote device to return messages.
    [00053] These various pull-ups can be used to provide other features in various embodiments of the present invention. For example, in some embodiments of the present invention, it may be useful to detect when a primary device is disconnected from one or more devices. For example, it may be desirable for a primary device to provide a disable signal to one or more devices when a primary device is turned off. But a host can be disconnected before being able to send such a signal. In this case, the absence of a pull-up on an LSR2PTX pin can be detected by a device and used by the device as an indication that it must be disconnected.
    [00054] Specifically, a main device can allow its pull-up on its LSR2PTX, while devices pull its pull-ups on its LSR2PTX pins down. If a device sees a pull-up on its LSP2R RX pin, it knows that it is connected to a primary device. It can then allow pull-up on the LSR2PTX pins on each of its ports, thereby informing daisy-connected devices that there is a host connected somewhere upstream. In this way, when the host is removed, the pull-up on the LSR2PTX is removed, and the device again pulls its LSR2PTX pull-ups down, thereby informing the daisy-connected devices that the host has been disconnected.
    [00055] As shown in this figure, the power received at pin 20 in a connector is provided at pin 1 of the remote connector. This prevents power sources from devices connected at each end of the cable from competing with each other. In contrast, the power on pin 20 of a first connector is supplied to a second connector on pin 1.
    [00056] In the exemplary cable in figure 5, a single data path in each direction is shown. In other embodiments of the present invention, two or more signal paths can be included. An example is shown in the following figure.
    [00057] Figure 6 illustrates an active cable according to an embodiment of the present invention. Again, only the circuitry associated with the high-speed paths is shown for simplicity. In this example, additional clock and data recovery circuits 615 and 635 were added to active plug 600, while clock and data recovery circuits 645 and 665 were added to active plug 605.
    [00058] In this and other embodiments of the present invention, the circuitry in the plugs can be connected by one or both devices being connected by the cable. For example, a main device connected to plug 600 can supply power to plugs 600 and 605, as well as a host connected to plug 605. In other examples, a device connected to plug 605 can receive a high voltage from a host connected to plug 600 , the device can supply power to plugs 600 and 605. In still other examples, a host connected to plug 600 can supply power to plug 600 and a device connected to plug 605 can supply power to plug 605. Specific examples can be found in the order United States Patent No. 13 / 173,979, entitled Distribution of Energy within the Cable, which is incorporated by reference.
    [00059] Again, the modalities of the present invention allow signals sharing pins between the two patterns so as not to interfere with each other. Consequently, the embodiments of the present invention employ circuit components to help isolate signal paths. Examples are shown in the following figures.
    [00060] Figures 7A to 7C illustrate circuits that can be used to allow signal paths of two different patterns to share common pins of a connector. In various embodiments of the present invention, these circuits can be located in, or associated with, a connector receptacle, connector insertion, or both. In figure 7A, an HSIO output can share a pin with a DisplayPort output. In this case, both outputs can be AC coupled through a capacitor to provide DC isolation from each other. Capacitors can be connected via a resistor network as shown to a connector pin. This resistor network degrades signal levels at 6 dB, but provides 12 dB of isolation.
    [00061] In figure 7B, a high-speed input and a configuration input can share a connector pin. In this case, the high speed receiving path can be AC coupled to provide isolation to the DC voltage at the configuration pin. The configuration pin can be isolated via a resistor. An additional capacitor can be included to provide additional filtration, as shown. In other embodiments of the present invention, the configuration pin can be directly coupled to the connector pin.
    [00062] In figure 7C, a high speed input can share a pin with an auxiliary input. Again, the high speed input can be AC coupled to provide a DC block. The auxiliary pin can be isolated via an inductor (such as high speed signals at 70 Mbps at 10 Gbps), while allowing DC or low frequency signals (such as signals at 1 MHz or less) to pass. Again, an additional capacitor can be added to provide additional filtration, as shown. Also, the auxiliary input can be AC coupled, as shown.
    [00063] Figures 8A and 8B illustrate alternating circuits that can be used to allow signal paths of two different patterns to share common pins of a connector. In various embodiments of the present invention, these circuits can be located in, or associated with, a connector receptacle, a connector insert, or both. In figure 8A, an HSIO output can share a pin with a DisplayPort output. In this example, both outputs can be AC coupled through capacitors C1 and C2 to provide DC isolation from each other. Capacitors C1 and C2 can be coupled via PiN diodes D1 and D2 to a connector pin.
    [00064] Specifically, when the high speed output is active, the HSBIAS high speed bias signal is active, triggering the output of the high B3 buffer. This polarizes the PiN D1 diode and connects capacitor C1 to a connector pin. Actuator B1 drives an output signal through capacitors C1 and diode D1 to the connector pin.
    [00065] When the DisplayPort output is active, the DisplayPort DPBIAS bias signal is active, triggering the output of the high B4 buffer. This polarizes the PiN D2 diode, so that it turns on and connects an output from capacitor C2 to the connector pin. Actuator B2 can then drive a signal through capacitor C2 and diode D2 to the connector pin.
    [00066] When the high speed output is active, care must be taken to avoid reflections through the DisplayPort path that can interfere with the output signal such as the connector pin. For this reason, an embodiment of the present invention can include an attenuator P1 between capacitor C2 and diode D2 as shown. This attenuator P1 can be formed from a pi resistor or T-network or other appropriate attenuator.
    [00067] When the high speed output is active, signals on the connector pin can pass through diode D2, which is off, then through attenuator P1 and capacitor C2, thereby appearing on an output of the DisplayPort B2 buffer, the which is off. Although the DisplayPort B2 trigger is sometimes off, some signal may reflect on its output, and move forward again through capacitor C2, attenuator P1, and diode D2, appearing on the connector pin and interfering with the desired signal.
    [00068] In a specific embodiment of the present invention, an off diode D2 provides approximately 6 dB of attenuation to the return signal. The attenuator P1 can provide an additional attenuation of 4 dB, while the DisplayPort B2 buffer can provide an additional 10 dB of signal reduction as it reflects the signal and sends it forward. As the signal moves forward, it encounters the attenuator P1 and diode D2, and is again reduced by the attenuation of the same. In this way, reflected signals pass through the attenuator P1 twice, and are thus attenuated twice. When the DisplayPort B2 output is active, the attenuator P1 attenuates the signal, but only once. Consequently, in various embodiments of the present invention, the DisplayPort B2 buffer has an increased actuation force to justify the loss due to the attenuator P1.
    [00069] In a specific embodiment of the present invention, the high speed output is approximately twice as fast as the DisplayPort output. In such a situation, an attenuator, such as P1, is not required in the high-speed transmission path, although it may be included.
    [00070] In several examples, like figure 8A, the signal paths are shown as single termination for clarity. In various embodiments of the present invention, the signal paths can be single or differential terminated.
    [00071] In figure 8B, a high speed input can share a pin with an auxiliary input. As before, the high speed input can be AC coupled by a capacitor C1 to supply a DC block. The auxiliary input pin can be isolated via the L1 inductor, which can block AC signals while allowing DC signals to pass. An additional capacitor C2 may be included to provide additional filtration, as shown. As before, the auxiliary signal path can be AC coupled through capacitor C3, as shown.
    [00072] In some embodiments of the present invention, the auxiliary signal can be an I2C signal. In such a case, charging caused by capacitors C1 and input resistance of buffer B1 may be sufficient to overload the driver by supplying the I2C signal and causing errors in the transmission of the I2C signal. Accordingly, the embodiments of the present invention can include a PiN D1 diode as shown. This PiN diode can be used to isolate capacitor C1 when it is not needed.
    [00073] Specifically, when I2C signals are received, the HSBIAS bias signal may be inactive (low), which triggers the output of the low B2 buffer. This, in turn, can turn off diode D1, thereby isolating the I2C signals from capacitor C1. The M1 multiplexer can select the I2C line.
    [00074] Similarly, when auxiliary signals are received, HSBIAS may again be low, which may isolate capacitor C1 from the auxiliary line. The multiplexer M1 can select the auxiliary signal path, which can again be coupled to AC via capacitor C3.
    [00075] When high speed signals are received, HSBIAS can be active (high), thereby triggering the output of the high B2 buffer. The multiplexer M1 can select resistor R3, which provides a return path for the current supplied through D1 to the output of buffer B2. This can turn on diode D1 and can attach a connector pin to capacitor C1 for receiving high speed signals.
    [00076] Several display screens may include a dedicated cable that is attached as part of the display screen. These can be referred to as stuck cables. Stuck cables can be used for DisplayPort monitors or HSIO monitors, among other types of monitors. Also, these cables can be driven by DisplayPort or HSIO sources. Consequently, it is desirable for these devices to be able to determine what they are connected to, so that they can configure themselves appropriately. An example of this is shown in the following figure.
    [00077] Figure 9 illustrates circuits and methods used by devices to determine what types of devices they are connected to. On line 910, a Displayport source or host communicates with a sink or entremity. Again, the configuration pins CFG1 and CFG2 are pulled to a low degree. The attached cables can be a passive cable, and the DisplayPort heatsink or end can function as a DisplayPort device.
    [00078] On line 920, a Displayport source or host communicates with an HSIO heatsink or end. Since the heatsink or end is an HSIO device, the attached cable is active. However, since the source or host is a DisplayPort device, the attached cable can operate in a bypass mode to save energy. That is, the clock and data recovery circuits included must be inactive. Since the HSIO heatsink or end does not detect the pull up on an LSx pin (which can be the LSR2P TX pin), it can work in a DisplayPort mode. The HSIO heatsink can also drive low CFG2.
    [00079] In line 930, the source or host is an HSIO device, while the heatsink or end is a DisplayPort device. The HSIO source or host provides pull downs on the CFG1 and CFG2 lines. In this example, the pull-down resistors have a value of 1 mega, although other resistors can be used according to the modalities of the present invention. The HSIO source or host determines that the voltage on the CFG2 configuration pin is low (that is, there is no pull-up), and that CFG1 is also low (consequently, the cable is not an adapter). Consequently, the HSIO source or host works in a DisplayPort mode.
    [00080] On line 940, an HSIO source or host communicates with an HSIO heatsink or end. As before, the HSIO source or host provides pulls up on an LSx pin, and pull downs on the CFG1 and CFG2 configuration pins. The HSIO heatsink or end detects the pull-up on the LSx pin, and consequently functions as an HSIO device. In this example, the heatsink or display screen provides a 100K pull-up on the CFG2, although in other embodiments of the present invention, other resistors of a certain size can be used. Consequently, the HSIO source or host detects that the voltage on the CFG2 pin is high, and consequently functions as an HSIO device.
    [00081] In a particular embodiment of the present invention, a attached cable has a plug that can include a circuitry, as well as a Y-cable, which can include an additional circuitry. In other embodiments of the present invention, all circuitry may be included in the plug or in the Y cable portion of the attached cable. An example is shown in the following figure.
    [00082] Figure 10 illustrates a set of circuits for a cable attached according to an embodiment of the present invention. A plug is provided for insertion into a connector, such as the connector shown in figure 2. The plug is attached to a plug on the Y cable portion, which connects to a Y cable housing portion, which includes additionally a set of circuits. From there, the Y-cable attaches to a multi-layer monitor board.
    [00083] In this example, high-speed signals are received by the monitor via the clock and 1010 and 1030 data recovery circuits, which can be located in a Y cable housing. The outputs of that clock and these recovery circuits data is provided for the clock and data recovery circuits 1020 and 1040. The clock outputs and data recovery circuits 1020 and 1040 are provided by diodes PiN D1 to D4 as HSIO or DisplayPort signals. Note that the polarization resistors for the diodes PiN D1 to D4 in this figure have been omitted for clarity. Again, when the cable is acting to provide DisplayPort signals, the clock and data recovery circuits can operate in a bypass mode to save energy. Similarly, the high speed signals provided from the watch and data recovery circuits from the monitor 1050 1 1070 are received and supplied to the connector via the watch and data recovery circuits 1060 and 1080 on the plug. The signals can be isolated as shown.
    [00084] In the example shown, the diodes PiN D1 to D4 are used to isolate HSIO and DisplayPort signals. In other embodiments of the present invention, resistors, multiplexers or other circuits or components can be used.
    [00085] In various embodiments of the present invention, the security and accuracy of data connections can be improved by calibrating or training circuitry on hosts, cables and other devices. Such circuitry may include circuits to compensate for oblique cable, crossover (particularly in a connector), channel compensation (such as equalization or concelation of reflections), and other similar circuitry. These circuits can be adjusted using various parameters. In various embodiments of the present invention, parameters for these circuits can be calibrated or otherwise determined by manufacture and stored as gifts for charging during operation. In other embodiments of the present invention, these parameters can be determined while the system is connected. This training or calibration can occur during power up, restart, or other periodic or time-based event. These and other routines can be used to calibrate the path from a host to an end near the cable, the path through the cable, and the path from the cable to a device or other host.
    [00086] This calibration can be performed in several ways. For example, a host can place one end of the cable in loopback mode, transmit data, and receive data, and then adjust the receive and transmit parameters accordingly. Similarly, a device can place its end close to the cable in loopback mode, transmit data, and receive data, and then adjust receive and transmit parameters accordingly. Either or both the host or the device can also place its far end in loopback mode, thereby including the cable in the calibration routine. An example is shown in the following figure.
    [00087] Figure 11 illustrates a method of calibrating a cable and related circuitry according to one embodiment of the present invention. In act 1110, the calibration or training procedure begins. This can be triggered by an energization, cable connection, restart condition or other periodic or event-triggered criteria. In act 1120, an end close to the cable is arranged in loopback mode. A signal is transmitted and received via the loopback path in act 1130. Receive and transmit parameters for near-end circuits can be improved in act 1140. In act 1150, the distant end of the cable can be arranged in loopback mode. Again, a signal can be transmitted and received through this loopback path in act 1160. Receiving and transmitting parameters for far-end circuits can be improved in act 1170. This procedure can be performed by either or both the host and the circuits device.
    [00088] The above description of the modalities of the invention has been presented for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the invention to the precise form described, and many modifications and variations are possible in light of the above teachings. The modalities were chosen and described in order to better explain the principles of the invention and its practical applications, thus allowing other people skilled in the art to better use the invention in the various modalities and with the various modifications that are suitable for the particular use contemplated. Thus, it will be appreciated that the invention is intended to cover all modifications and equivalents within the scope of the embodiments.
    权利要求:
    Claims (22)
    [0001]
    1. Active cable (225, 235), comprising: a cable (507); a first plug (500) connected to a first end of the cable (507), and a second plug (505) connected to a second end of the cable (507), the active cable (225, 235) characterized by the fact that: o first plug (500) comprises: a first clock and data recovery circuit (510) to retemporize signals received at an input of the first plug (500); a second clock and data recovery circuit (530) to retemporize signals received from the cable (507); and a first microcontroller (520) for configuring the first clock and data recovery circuit (510) and the second clock and data recovery circuit (530); and a second plug (505) connected to a second end of the cable (507) and comprising: a third clock and data recovery circuit (540) to retemporize signals received at an input of the second plug (505); a fourth clock and data recovery circuit (560) to retemporize signals received from the cable (507); a second microcontroller (550) for configuring the third clock and data recovery circuit (540) and the fourth clock and data recovery circuit (560).
    [0002]
    2. Active cable (225, 235) according to claim 1, characterized in that the cable (507) connects an output of the first clock and data recovery circuit (510) to an input of the fourth clock and circuit data recovery (560) and an output of the third clock and data recovery circuit (540) to an input of the second clock and data recovery circuit (530).
    [0003]
    3. Active cable (225, 235), according to claim 1, characterized by the fact that the first microcontroller (520) and the second microcontroller (550) are programmable using pins on the first plug (500) and the second plug ( 505).
    [0004]
    4. Active cable (225, 235) according to claim 1, characterized by the fact that the first clock and data recovery circuit (510) includes an equalizer circuit.
    [0005]
    5. Active cable (225, 235) according to claim 1, characterized by the fact that the first clock and data recovery circuit (510) comprise a de-emphasis circuit.
    [0006]
    6. Active cable (225, 235), according to claim 1, characterized by the fact that the first microcontroller (520) can configure an output of the first clock and data recovery circuit (510) to couple with an input of the second clock and data recovery circuit (530).
    [0007]
    7. Active cable (225, 235), according to claim 1, characterized by the fact that the first microcontroller (520) can configure an output of the second clock and data recovery circuit (530) to be coupled to an input of the first clock and data recovery circuit (510).
    [0008]
    8. Cable assembly, comprising: a cable (507); a first plug (500) coupled to a first end of the cable (507) and comprising first circuitry for receiving and transmitting signals; and a second plug (505) coupled to a second end of the cable (507) and comprising a second set of circuits for receiving and transmitting signals, characterized by the fact that: when the cable (507) conducts signals according to a first protocol, the first circuitry and the second circuitry are driven, and when the cable (507) conducts signals according to a second protocol, the first circuitry and the second circuitry are not driven.
    [0009]
    Cable assembly according to claim 8, characterized in that the first circuit assembly comprises a first clock and data recovery circuit (510) having an input coupled to the pins of the first plug (500) and a second clock and data recovery circuit (530) coupled to conductors on the cable (507).
    [0010]
    10. Cable assembly according to claim 9, characterized by the fact that it still comprises a microcontroller (520) to configure the first clock and data recovery circuit (510) and the second clock and data recovery circuit ( 530).
    [0011]
    11. Cable assembly according to claim 10, characterized in that the microcontroller (520) can be programmed using at least one pin from the first plug (500).
    [0012]
    Cable assembly according to claim 11, characterized in that the microcontroller (520, 550) can be programmed using code provided on at least one pin of the first plug (500).
    [0013]
    13. Cable assembly according to claim 12, characterized by the fact that the code is encrypted.
    [0014]
    14. Connector and signal path circuit for an electronic device comprising: the connector (500) including a plurality of pins; a first output circuit coupled to a first pin (HSOTX) in the plurality of pins and characterized by the fact that it comprises: a selection circuit (D1, D2) coupled to the first pin (HSOTX); a first AC driver (B1) coupled to the selection circuit (D1, D2); and a second AC driver (B2) coupled to an attenuator (P1), the attenuator (P1) coupled to the selection circuit (D1, D2).
    [0015]
    15. Connector and signal path circuit according to claim 14, characterized by the fact that the connector is a connector insert (500).
    [0016]
    16. Connector and signal path circuit according to claim 14, characterized by the fact that the connector is a connector receptacle.
    [0017]
    17. Connector and signal path circuit according to claim 14, characterized by the fact that the attenuator (P1) is a pi network.
    [0018]
    18. Connector and signal path circuit according to claim 14, characterized in that the selection circuit (D1, D2) comprises a plurality of PiN diodes (D1, D2).
    [0019]
    19. Connector and signal path circuit according to claim 14, characterized by the fact that the selection circuit (D1, D2) comprises a multiplexer.
    [0020]
    Connector and signal path circuit according to claim 14, characterized in that it additionally comprises a reception circuit comprising: a first switch (D1) having a first terminal coupled to the second pin (HS1RX) in plural of pins; a receiving circuit (B1) AC coupled to the second terminal of the first switch (D1); an inductor (L1) having a first terminal coupled to the second pin; and a capacitor (C2) coupled between a second inductor terminal (L1) and the ground.
    [0021]
    21. Connector and signal path circuit according to claim 20, characterized by the fact that it still comprises a multiplexer (MUX M1) coupled to the second terminal of the inductor (L1).
    [0022]
    22. Connector and signal path circuit according to claim 20, characterized in that the switch (D1) comprises a PiN diode.
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    公开号 | 公开日
    CN202308695U|2012-07-04|
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    WO2012003381A2|2012-01-05|
    JP2013242873A|2013-12-05|
    US20120005496A1|2012-01-05|
    CN102315576A|2012-01-11|
    HK1166666A1|2012-11-02|
    CN102332667B|2015-02-18|
    US20130173936A1|2013-07-04|
    CN104733966B|2018-08-21|
    KR101720398B1|2017-03-27|
    CN104317376B|2017-04-12|
    CN104733966A|2015-06-24|
    KR20140060588A|2014-05-20|
    KR101758968B1|2017-07-17|
    CN102332667A|2012-01-25|
    US8516238B2|2013-08-20|
    US8862912B2|2014-10-14|
    KR101474097B1|2014-12-17|
    EP2588933B1|2017-03-29|
    JP2013539332A|2013-10-17|
    EP2589042A2|2013-05-08|
    EP2588933A1|2013-05-08|
    US20120000705A1|2012-01-05|
    KR101449229B1|2014-10-08|
    US8312302B2|2012-11-13|
    US9274579B2|2016-03-01|
    JP5903401B2|2016-04-13|
    JP2013513193A|2013-04-18|
    US20140344615A1|2014-11-20|
    KR20140105601A|2014-09-01|
    US20120233489A1|2012-09-13|
    JP5241964B2|2013-07-17|
    US8683190B2|2014-03-25|
    CN202797544U|2013-03-13|
    JP5283787B1|2013-09-04|
    US20140359319A1|2014-12-04|
    BR112012030352A2|2017-06-20|
    CN104317376A|2015-01-28|
    US9494989B2|2016-11-15|
    WO2012003385A1|2012-01-05|
    CN102315576B|2014-08-06|
    KR20130031841A|2013-03-29|
    WO2012003381A3|2012-03-15|
    KR20130046399A|2013-05-07|
    EP2589042B1|2019-03-13|
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    法律状态:
    2018-12-26| B06F| Objections, documents and/or translations needed after an examination request according art. 34 industrial property law|
    2019-11-12| B06U| Preliminary requirement: requests with searches performed by other patent offices: suspension of the patent application procedure|
    2020-06-30| B06A| Notification to applicant to reply to the report for non-patentability or inadequacy of the application according art. 36 industrial patent law|
    2020-10-13| B09A| Decision: intention to grant|
    2020-12-29| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 30/06/2011, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    US36043210P| true| 2010-06-30|2010-06-30|
    US36043610P| true| 2010-06-30|2010-06-30|
    US61/360,432|2010-06-30|
    US61/360,436|2010-06-30|
    US201161446027P| true| 2011-02-23|2011-02-23|
    US61/446,027|2011-02-23|
    PCT/US2011/042684|WO2012003381A2|2010-06-30|2011-06-30|Circuitry for active cable|
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